Lateral nanostructures by vertical processing

ABSTRACT

The present invention is directed to a process for forming one or more lateral nanostructures on a substrate. The process comprises the steps of: providing a substrate; depositing a first layer on the substrate; forming at least one edge on the first layer; depositing at least one separation layer on the first layer; depositing a third layer on the separation layer; and removing a portion of the separation layer and the third layer from the substrate such that a substantially planar surface is formed exposing the first layer, the separation layer, and the third layer.

[0001] This application claims priority from U.S. ProvisionalApplication No. 60/280,235, filed Mar. 30, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to lateral nanostructures. Moreparticularly, the present invention relates to lateral nanostructuresformed by vertical processing on a substrate.

[0004] 2. Description of the Prior Art

[0005] Nanoscale structures are of interest for a wide variety of deviceand material investigations. The need to develop such nanostructures iswell recognized in the art (Science, Vol. 294, December 2001; C. Zhou,M.R. Deshphande, M. A. Reed, L. Jones II and J. M. Tour, NanoscaleMetal/Self-Assembled Monolayer/Metal Heterostructures, Appl. Phys. Lett.71 (5), August 1997; Tseng and Ellenbogen, Toward Nonocomputers,Science, Vol. 294, November 2001). Nanoscale structures are typicallydefined using nanolithography techniques. These techniques includeeither traditional techniques such as electron beam, x-ray, or advancedoptical lithography, or alternative lithographic techniques such asmicro- or nano-stamping or contact printing, or scanning probelithography. However, the resolution of each of these techniques islimited and none is able to routinely achieve extreme nanoscale ormolecular scale dimensions.

[0006] A prior art approach to forming nanostructures is depicted inFIG. 1. Here a multi-layer structure 10 with a center region 12 ofnanothickness separating two thicker regions 14,16 is used. All threelayers 12,14,16 can be deposited by a variety of deposition techniques,such as evaporation, sputtering, or chemical vapor deposition. Thecenter region 12 can be of any desired thickness down to atomicdimensions.

[0007] However, an important prior art limitation exists in that thedefect density for ultrathin separation layers is typically quite large.In the case of conductors or semiconductors separated by a thininsulating layer, this defect density creates short circuits betweenlayers unless the multi-layer area is limited to very small dimensions.Thus, this approach often requires nanolithography even though the layerseparation is created by deposition. This in turn makes it difficult toconnect contacts or wiring to the small area nanostructure since suchconnections must also be nanoscale. In addition, the nanostructureformed as described is vertical, that is, the nano-dimension is in thedirection normal to the substrate. For many applications lateralnanostructures are required or desirable.

[0008] Therefore, there clearly is a need in the art for a process tofabricate lateral nanostructures on substrates, such as conductors orsemiconductors with virtually no defects, no short circuits andpreferably by means other than nanolithography. This need in the art issatisfied by the present invention, which provides a process for forminglateral nanostructures using primarily vertical processing. Theresulting nanostructures are virtually defect free and thus do notrequire further processing.

SUMMARY OF THE INVENTION

[0009] The present invention provides a process for forming a lateralnanostructure on a substrate. The process comprises the steps of:

[0010] (a) providing a substrate;

[0011] (b) depositing a first layer on the substrate;

[0012] (c) forming at least one edge on the first layer;

[0013] (d) depositing at least one separation layer on the first layer;

[0014] (e) depositing a third layer on the separation layer; and

[0015] (f) removing a portion of the separation layer and the thirdlayer such that a substantially planar surface is formed exposing thefirst layer, the separation layer, and the third layer.

DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a perspective view of a prior art nanostructure;

[0017]FIGS. 2a-d are perspective views of a lateral nanostructure duringvarious process stages according to the process of the presentinvention;

[0018]FIG. 3a is a perspective view of a lateral nanostructure formedfrom the process of the present invention;

[0019]FIG. 3b is an exploded view of the lateral nanostructure depictedin FIG. 3a with a schematically represented molecule placed across thenanostructure;

[0020]FIG. 4 is a perspective view of a nanostructure formed from theprocess of the present invention with a caltrops molecule selectivelyattached thereto;

[0021]FIGS. 5a-e are perspective views of a lateral nanostructure atvarious process steps according to the present invention; and

[0022]FIG. 6 is a perspective view of a lateral nanostructure having twoseparation layers formed according to the process of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention is directed to a process for fabricatinglateral nanostructures using primarily vertical processing. Referring tothe Figures and, in particular, FIGS. 2a-d, the process of the presentinvention is generally illustrated.

[0024] Referring to FIG. 2a, a substrate 20 is depicted having a layer22. Suitable substrates for use with the present invention include, forexample, glass, silicon dioxide, polymeric materials, semiconductorssuch as silicon, germanium, silicon germanium, gallium arsenide,aluminum arsenide, silicon carbide, gallium nitride, aluminum nitride,indium nitride, indium phosphide, indium arsenide, metals, and anycombinations thereof.

[0025] Layer 22 can be deposited or created on substrate 20 by anysuitable process, including, for example, evaporation, sputtering,chemical vapor deposition, oxidation, anodization, ion beam deposition,electrodeposition, plasma deposition, or any combinations thereof.Suitable materials for forming layer 22 include, for example,dielectrics such as silicon dioxide, silicon nitride, aluminum oxide,metals, semiconductors, organic materials, or any combinations thereofand may include multilayers. Alternatively, layer 22 may be omitted ifit is desired to form the nanostructure directly on substrate 20.

[0026] The process of the present invention begins by depositing a firstlayer 24 on layer 22 such that an edge 26 is created. First layer 24 canbe deposited or created on layer 22 by any suitable process, including,for example, evaporation, sputtering, chemical vapor deposition,oxidation, anodization, ion beam deposition, electrodeposition, plasmadeposition, or any combinations thereof. Suitable materials for formingfirst layer 24 include, for example, copper, gold, aluminum, nickel,platinum, palladium, silver, titanium, tantalum, niobium, hafnium,chromium, other metals, semiconductors, insulators, organic materials,or any combinations thereof.

[0027] Edge 26 can be formed by any suitable technique or process.Suitable processes for forming edge 26 include, for example, etching,depositing using a mask technique, such as, for example, lift-offpatterning, scribing, or any combinations thereof It should beunderstood that it is not essential that the profile of edge 26 bevertical. It should also be understood that two or more edges 26 may beformed in layer 24.

[0028] Referring to FIG. 2b, a second layer or separation layer 28 isdeposited or created on first layer 24. Separation layer 28 can bedeposited or created by any suitable process including, for example,evaporation, sputtering, chemical vapor deposition, oxidation,anodization, ion beam deposition, electrodeposition, plasma deposition,or any combinations thereof. Suitable materials for forming separationlayer 28 include, for example, silicon dioxide, silicon nitride,aluminum oxide, glass, other insulators, metals, semiconductors, organicmaterials, or any combinations thereof.

[0029] Depending on the process used to create first layer 24,separation layer 28 may cover both the surface of first layer 24 and theadjacent surface of layer 22 or only the surface of first layer 24.Separation layer 28 can be either conformal (same thickness everywhere)or non-conformal (different thickness in different regions).

[0030] Referring to FIG. 2c, a third layer 30 is deposited or created onseparation layer 28. Third layer 30 can be deposited or created by anysuitable process including, for example, evaporation, sputtering,chemical vapor deposition, oxidation, anodization, ion beam deposition,electrodeposition, plasma deposition, or any combinations thereof.Suitable materials for forming third layer 30 include, for example,copper, gold, aluminum, nickel, platinum, palladium, silver, titanium,tantalum, niobium, hafnium, chromium, other metals, semiconductors,insulators, organic materials, or any combinations thereof.

[0031] Referring to FIG. 2d, a planarization technique is used to removethe excess second layer 30 and a portion of separation layer 28 tocreate the lateral nanostructure 32, in which all three layers 24, 28,30 are exposed. Any suitable planarization technique can be used.Suitable planarization techniques include, for example,chemical-mechanical polishing (CMP), organic reflow and etchback,inorganic reflow and etchback, or any combinations thereof Referring toFIG. 3 a, structure 40 is depicted with a small area, lateralnanostructure 32, completed by a simple patterning technique. Becausethe vertical extent of the nanostructure can be controlled to a verysmall dimension, typically about 1 nm to about 10,000 nm, by depositionand removal processes, it is easy to create small area nanostructureseven when fairly crude, for example, micron-scale patterning is used forthis final step. If nanolithograpy is used, extremely small areas arepossible, if desired. In addition, connections to lateral nanostructurescreated by this technique are readily and naturally obtained and may beincluded as part of the final patterning step as shown.

[0032] Referring to FIG. 3b, a molecule 34 is depicted as beingselectively attached to layers 24, 30 of the lateral nanostructure 32,on each side of separation layer 28.

[0033] With the process of the present invention, the separation layer28 can be formed such that the first layer 24 and third layer 30 areseparated by a width of secondary layer 28 with nanoscale dimension.Widths as small as 1 nm, or even smaller, are in principle possible,with sub-nanometer control of the dimension from about 1 nm to about1000 nm or even greater.

[0034] The present invention can be further understood by the followingexamples.

EXAMPLE 1

[0035] The process of the present invention can be used to createlateral nanostructures with dimensions ranging from atomic scale to anydesirable larger size. Such lateral nanostructures are useful for makingmultiple connections to molecules and other nanosize devices. By way ofexample, referring to FIG. 4, a separation region 32 of a lateralnanostructure with a caltrops molecule 50 selectively attached todifferent metals 24,30 on each side of the separation region 32, isillustrated. A scanning tunneling microscope tip 52 is shown approachingthe caltrops molecule 50 so that three-terminal measurements ofmolecular characteristics can be made.

EXAMPLE 2

[0036] The process of the present invention can be used to form alateral nanogap test bed. Controllably positioning two electrodes withina few tens of angstroms from one another is not a trivial task.Non-optical lithography techniques, such as electron-beam lithographyand x-ray lithography, have maximum resolutions near 15 nm. Therefore,these techniques used in a conventional manner, cannot provide the meansof creating a 2 nm gap. However, thin films can be deposited withangstrom thickness resolution. In the lateral nanogap fabricationprocess, a thin-film dictates this electrode spacing rather thanlithography.

[0037] The following example demonstrates a process for forming aPt/Al₂O₃/Au lateral nanogap test bed.

[0038] The first step to creating the lateral nanogap test bed is toselect an appropriate substrate 60. For convenience a silicon wafer isused. A thick oxide is grown to minimize coupling between the electrodesthrough the substrate. Double-layer lithography is performed to definethe regions where the first metal will be removed following deposition.A 5 nm chromium adhesion layer 62 and a 50 nm platinum layer 64 areion-beam deposited. Platinum has a very low CMP removal rate in nearlyall slurries and is an excellent material for molecular self-assembly.Metal lift-off is performed by first soaking the substrate in a warmacetone bath followed by subsequent ultrasonic cleanings, one in cleanacetone and the other in isopropyl alcohol. FIG. 5a shows the structureat this point in processing. Residual photoresist is removed in anoxygen plasma.

[0039] As illustrated in FIG. 5b, a thin dielectric spacer 66 isdeposited either by plasma-enhanced chemical-vapor deposition (PECVD) orion-beam sputtering. A low-deposition rate (0.02 nm/s) is attainablewhen depositing a dielectric by ion-beam sputtering. This element ofcontrol is important when using a deposition to define a criticaldimension. Aluminum oxide is chosen based on its ability to adhere to aninert surface such as that of platinum. To improve sidewall coverage,the substrate holder is heated to 80° C. and rotated during deposition.

[0040] As depicted in FIG. 5c, a 100 m gold layer 68 is depositedfollowing the deposition of a 2 nm chromium adhesion layer (not shown).

[0041] As illustrated in FIG. 5d, once the gold layer 68 has beendeposited, it is removed down to the chromium adhesion layer by chemicalmechanical polishing (CMP). The CMP polishing slurry is made bycombining a dilute gold etch [210 g H₂O: 2.05 g KI: 1.03 g I₂] with 0.03μm alumina abrasive. Both the polishing pad and chuck (not shown) arerotated counter clockwise with a down-force of 50 N. The averagepolishing rate of gold is approximately 5 nm/s while that of platinum isnearly zero. CMP was performed using a Struers Abramatic polishingsystem.

[0042] After substrate 60 is removed from the polishing chuck andcleaned, the second and final lithography step is performed. Thephotoresist is hardbaked at 135° C. for 10 min to make it more durablefor the subsequent processing. A 15 min ion-milling operation is done insteps of 2 min separated by 3 min breaks. This will prevent excessivelocal heating and preserve the photoresist mask. Next, the photoresistis stripped in a strong solvent followed by an oxygen plasma etch. Achrome wet etch is then done to insure exposure of the dielectricspacer. The final step is a brief etch in warm H₂SO₄ to form a recess 72in the aluminum oxide 66. FIG. 5e depicts the final structure.

[0043] It should be understood that while the invention is depictedabove as a substrate having only one lateral nanostructure, thesubstrate can just as easily be formed with two or more lateralnanostructures on a single substrate. Since patterned features typicallyhave two or more edges, forming two or more lateral nanostructures onthe substrate is as simple as forming one. Arrays and the like are alsopossible, with spacing set by whatever lithographic technique is used.

[0044] It should also be understood that the separation layer of thepresent invention depicted above, in the middle of the lateral nanogapstructure, does not need to be a single material. Multiple separationlayers may be formed in the same manner described for forming the singleseparation layer, as noted above. In addition, the multiple separationlayers may be formed from the same material noted above for the singleseparation material. By way of example, referring to FIG. 6, a substrate80 having two separation layers 82, 84 formed between a first layer 86and a second layer 88, is depicted. Each separation layer may be formedto have a width of about 1 nm to about 1000 nm.

[0045] It is also possible to repeat the process of the presentinvention to form new lateral nanostructures on top of those lateralnanostructures formed earlier or at their edges.

[0046] It should be understood that the foregoing description andexamples are only illustrative of the present invention. Variousalternatives and modifications can be devised by those skilled in theart without departing from the invention. Accordingly, the presentinvention is intended to embrace all such alternatives, modificationsand variances.

What is claimed is:
 1. A process for forming one or more lateralnanostructures on a substrate comprising the steps of: (a) providing asubstrate; (b) depositing a first layer on said substrate; (c) formingat least one edge on said first layer; (d) depositing at least oneseparation layer on said first layer; (e) depositing a third layer onsaid separation layer; and (f) removing a portion of said separationlayer and said third layer such that a substantially planar surface isformed exposing said first layer, said separation layer, and said thirdlayer.
 2. The process of claim 1, wherein said substrate is selectedfrom the group consisting of: glass, silicon dioxide, polymericmaterials, semiconductors such as silicon, germanium, silicon germanium,gallium arsenide, aluminum arsenide, silicon carbide, gallium nitride,aluminum nitride, indium nitride, indium phosphide, indium arsenide,metals, and any combinations thereof.
 3. The process of claim 1, whereinsaid first layer is selected from the group consisting of: copper, gold,aluminum, nickel, platinum, palladium, silver, titanium, tantalum,niobium, hafnium, chromium, other metals, semiconductors, insulators,organic materials, and any combinations thereof.
 4. The process of claim1, wherein said first layer is deposited on said substrate by a meansselected from the group consisting of: evaporation, sputtering, chemicalvapor deposition, oxidation, anodization, ion beam deposition,electrodeposition, plasma deposition, and any combinations thereof. 5.The process of claim 1, wherein said edge is formed by a means selectedfrom the group consisting of: etching, masking, scribing, and anycombinations thereof.
 6. The process of claim 1, wherein said separationlayer is selected from the group consisting of silicon dioxide, siliconnitride, aluminum oxide, glass, other insulators, metals,semiconductors, organic materials, and any combinations thereof.
 7. Theprocess of claim 1, wherein said separation layer is deposited on saidfirst layer by a means selected from the group consisting of:evaporation, sputtering, chemical vapor deposition, oxidation,anodization, ion beam deposition, electrodeposition, plasma deposition,and any combinations thereof.
 8. The process of claim 1, wherein saidthird layer is selected from the group consisting of: copper, gold,aluminum, nickel, platinum, palladium, silver, titanium, tantalum,niobium, hafnium, chromium, other metals, semiconductors, insulators,organic materials, and any combinations thereof.
 9. The process of claim1, wherein said third layer is deposited on said separation layer by ameans selected from the group consisting of: evaporation, sputtering,chemical vapor deposition, oxidation, anodization, ion beam deposition,electrodeposition, plasma deposition, and any combinations thereof. 10.The process of claim 1, wherein said separation layer and said thirdlayer are removed by a planarization means.
 11. The process of claim 10,wherein said planarization means is selected from the group consistingof: chemical mechanical polishing, organic reflow and etchback,inorganic reflow and etchback, and any combinations thereof.
 12. Theprocess of claim 1, wherein said separation layer of said substantiallyplanar surface has a width of about 1 nm to about 1000 nm.